Integrated circuits (“ICs”) are typically fabricated on a substrate (“wafer”) of silicon or other semiconductor material. The substrate includes many ICs, which are separated into individual dies (“chips”). Modern ICs have many layers of patterned metallization, and millions of individual electronic devices, such as transistors, on each chip. Electrical interconnections between the devices and between functional blocks on the chip are made using metal traces and vias. However, as the dimensions of the patterned metal interconnections shrink, resistance-per-length increases, which increases delay and power consumption. Other problems, such as cross-coupling and electromagnetic interference (“EMI”) also arise.
One approach to remedy delay, or latency, is to more closely space electronic repeaters along an interconnect line. This is undesirable because repeaters take up area on the chip and consume additional power. Repeaters also make it more difficult to route signal lines.
Optical signaling has been proposed as an alternative to electrical interconnections for use in ICs. A basic optical signaling system is described in On-Chip Optical Interconnects by Kobrinsky et al., INTEL TECHNOLOGY JOURNAL, v. 8, issue 2 (May 10, 2004), the disclosure of which is hereby incorporated by reference in its entirety for all purposes. Optical signal networks can provide high-bandwidth, low-latency interconnects that are relatively immune to EMI. However, conventional on-chip optical signal networks were found to not reveal significant advantages over copper-based networks because certain optical components are not available for incorporation into a CMOS IC.
It is desirable to provide optical components for use in a CMOS IC that provides advantageous use of an on-chip optical network.